HAQ (Hardware-Aware Automated Quantization with Mixed Precision)
Algorithms AIMech:HAQHardwareAwareAutomatedQuantizationWithMixedPrecision DRAFT
Aliases: HAQ, Hardware-Aware Automated Quantization, Hardware-Aware Automated Quantization with Mixed Precision
HAQ (Hardware-Aware Automated Quantization with Mixed Precision) is an automated mixed-precision neural network quantization framework that models layer-wise bitwidth allocation for both weights and activations as a continuous-control reinforcement learning task solved by a Deep Deterministic Policy Gradient (DDPG) actor-critic agent: at each layer step k, the agent observes a 10-dimensional normalized layer state vector O_k, outputs a continuous action a_k in [0, 1] rounded to discrete bitwidth b_k in [b_min, b_max] (with sequential bitwidth reduction to satisfy direct hardware simulator latency, energy, or size constraints), applies KL-divergence-calibrated linear quantization (or k-means for size constraints), and updates its policy from one-epoch fine-tuned validation accuracy rewards.
Identity Notes & Concept Scope
Distinct from uniform fixed-bitwidth quantization (e.g., PACT or 8-bit integer quantization), distinct from Hessian-spectrum mixed-precision quantization such as Q-BERT (AIMech:QBERTHessianBasedUltraLowPrecisionQuantizationOfBERT) which relies on second-order sensitivity without hardware-in-the-loop latency/energy feedback, and distinct from AMC (AIMech:AMCAccelerationAndModelCompressionOnMobileDevicesWithRL) which uses DDPG to search continuous channel/fine-grained pruning sparsity ratios rather than mixed-precision weight and activation bitwidths.
Claims & Grounded Evidence
4 Claims
Mechanism
#haq-ddpg-layerwise-state-and-order-preserving-continuous-bitwidth-action
HAQ processes a neural network layer-by-layer (taking two steps per layer, one for weights and one for activations) using a 10-dimensional state vector O_k = (k, c_in, c_out, s_kernel, s_stride, s_feat, n_params, i_dw, i_{w/a}, a_{k-1}) (Eqs. 1-2) and maps a continuous DDPG action a_k in [0, 1] to discrete bitwidth b_k = round(b_min - 0.5 + a_k * (b_max - b_min + 1)) (Eq. 3), sequentially decrementing layer bitwidths whenever direct hardware latency, energy, or model-size budgets are exceeded.
Mechanism
#haq-kl-calibrated-linear-quantization-and-variance-reduced-bellman-update
For each layer k, HAQ linearly quantizes weights on [-c, c] (and non-negative ReLU activations on [0, c]) via quantize(w, a_k, c) = round(clamp(w, c)/s) * s with step size s = c / (2^{a_k - 1} - 1) (Eq. 4) by choosing c to minimize D_KL(W_k || quantize(W_k, a_k, x)) (Eq. 5), and updates the DDPG critic via the baseline-subtracted Bellman target Q_hat_k = R_k - B + gamma * Q(O_{k+1}, w(O_{k+1}) | theta^Q) with R = lambda * (acc_quant - acc_origin) (Eqs. 6-8).
Application
#haq-roofline-specialized-edge-vs-cloud-mixed-precision-policies
Across BISMO temporal FPGA edge/cloud accelerators and BitFusion spatial ASIC accelerators on ImageNet (MobileNet-V1, MobileNet-V2, ResNet-50), HAQ reduces inference latency by 1.4x-1.95x and energy consumption by ~1.9x with negligible accuracy loss compared to fixed 8-bit quantization, automatically assigning fewer activation bits to memory-bound depthwise convolutions on edge devices while assigning more bits to depthwise convolutions on compute-bound cloud devices.
Limitation
#haq-per-episode-retraining-and-hardware-simulator-dependency-limitation
Because HAQ fine-tunes the quantized network for one epoch after every RL episode to compute the reward signal R and queries a target hardware accelerator or simulator in the loop, policy exploration incurs multi-epoch retraining overhead and policies optimized for one hardware architecture are sub-optimal when deployed on another (Table 1).
⚠️ Curated Limitations & Negative Results
- Each RL exploration episode requires one epoch of SGD fine-tuning on a subset of training data to evaluate quantized accuracy reward R.
- Quantization policies specialized for one hardware accelerator (e.g., spatial BitFusion ASIC) do not transfer optimally to different hardware architectures (e.g., temporal BISMO cloud FPGA).
Artificial Intelligence Ontology (AIO) Grounding
Mapped AIO Classes
| AIO Target Class | Mapping Relation | Mapping Rationale |
|---|---|---|
AIO:ArtificialNeuralNetwork
Artificial Neural Network
|
broad_match | HAQ is an automated mixed-precision quantization method for deep neural network compression and hardware acceleration. |
Evidence Sources & Primary Literature
3 Sources| Source ID | Publication / Document | Type / Access | Reference & Checksum |
|---|---|---|---|
r818-primary-pdf
|
Kuan Wang, Zhijian Liu, Yujun Lin, Ji Lin, Song Han
|
primary paper
full_text
|
ID: https://arxiv.org/bibtex/1811.08886
sha256:ecbe91505650…
|
r818-arxiv-abs
|
Kuan Wang, Zhijian Liu, Yujun Lin, Ji Lin, Song Han
|
primary paper
abstract_only
|
ID: https://arxiv.org/abs/1811.08886
sha256:7c04975f06ff…
|
r818-metadata-cr
|
Kuan Wang, Zhijian Liu, Yujun Lin, Ji Lin, Song Han
|
primary paper
abstract_only
|
ID: https://arxiv.org/bibtex/1811.08886
sha256:1a2885363496…
|
Ontology & Grounding Topology
Open in interactive network graph →Curation Provenance
Curator: Antigravity
Method: ai_assisted
Model: Gemini
Created: 2026-10-19T15:01:00Z
Updated: 2026-10-19T15:01:00Z
Source File:
data/curated/HAQHardwareAwareAutomatedQuantizationWithMixedPrecision.yaml
· Schema:
curated_concept.yaml
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